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ds04-21378-2e fujitsu semiconductor data sheet assp single serial input pll frequency synthesizer on-chip 2.5 ghz prescaler mb15e07sr description the fujitsu mb15e07sr is a serial input phase locke d loop (pll) frequency synthesizer with a 2.5 ghz prescaler. the 2.5 ghz prescaler has a dual modulus di vision ratio of 32/33 or 64/65 enabling pulse swallowing operation. the supply voltage range is between 2.7 v and 5.0 v. a refined charge pump supplies well-balanced output currents of 1.0 ma and 4.0 ma. the charge pum p current is selectable by serial data. the phase noise of mb15e07sr was drastically improved comparing wuth the former single pll, mb15e07sl. the data format of serial data and the pin assignments except for p, r and oscout pins are same as the former one, so it is easy to replace the former one. mb15e07sr is ideally suited for the base station of gsm (global system for mobile communications) and pcs. features ? high frequency operation: 2.5 ghz max low power supply voltage: v cc = 2.7 v to 5.0 v ultra low power supply current:i cc = 8.0 ma typ (v cc = vp = 3.75 v, ta = +25 c, in locking state) direct power saving function:power supply current in power saving mode typ 0.1 a (v cc = vp = 3.75 v, ta = +25 c) dual modulus prescaler: 32/33 or 64/65 (continued) packages 16-pin plastic tssop (fpt-16p-m07) 16-pad plastic bcc (lcc-16p-m06)
mb15e07sr 2 (continued) serial input 14-bit programmable reference divider: r = 3 to 16,383 serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 software selectable charge pump current on-chip phase control for phase comparator built-in digital locking detector circui t to detect pll lo cking and unlocking operating temperature: ta = ?40 c to +85 c pin assignments osc in n.c. v p v cc d o gnd xfin fin n.c. n.c. ld/fout n.c. ps le data clock 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 n.c. v p v cc d o gnd xfin n.c. ld/fout n.c. ps le data osc in n.c. fin clock 1 2 3 4 5 678 9 10 11 12 13 14 15 16 (fpt-16p-m07) (lcc-16p-m06) 16-pin tssop 16-pad bcc top view top view
mb15e07sr 3 pin descriptions pin no. pin name i/o descriptions tssop bcc 116osc in i programmable reference divider input. connection to a tcxo. 2 1 n.c. ? no connection. 32v p ? power supply voltage input for the charge pump. 43v cc ? power supply voltage input. 54d o o charge pump output. phase of the charge pump can be sele cted via programming of the fc bit. 6 5 gnd ? ground. 7 6 xfin i prescaler complementary input, which should be grounded via a capacitor. 87fini prescaler input. connection to an external vco should be done via ac coupling. 98clocki clock input for the 19-bit shift register. data is shifted into the shift regi ster on the rising edge of the clock. (open is prohibited.) 10 9 data i serial data input using binary code. the last bit of the data is a c ontrol bit. (open is prohibited.) 11 10 le i load enable signal input . (open is prohibited.) when le is set high, the data in the sh ift register is transferred to a latch according to the control bit in the serial data. 12 11 ps i power saving mode control. this pin must be set at ?l? at power-on. (open is prohibited.) ps = ?h?; normal mode ps = ?l?; power saving mode 13 12 n.c. ? no connection. 14 13 ld/fout o lock detect signal output (ld)/phas e comparator monitoring output (fout). the output signal is selected vi a programming of the lds bit. lds = ?h?; outputs fout (fr/fp monitoring output) lds = ?l?; outputs ld (?h? at locking, ?l? at unlocking.) 15 14 n.c. ? no connection. 16 15 n.c. ? no connection.
mb15e07sr 4 block diagram fin ps osc in d o clock le ld / fout xfin gnd sw v p c n t fp (16) (11) (10) (6) (9) (8) (7) (5) (13) (2) (4) 14 3 5 6 8 9 10 7 11 12 1 (3) 4 data v cc 7-bit latch 11-bit latch sw fc lds cs reference oscillator circuit binary 14-bit reference couter 14-bit latch 4-bit latch phase comparator lock detector 19-bit shift register intermittent mode control (power save) 1-bit control latch binary 7-bit swallow counter binary 11-bit programmable counter prescaler 32/33 64/65 fr charge pump ld/fr/fp selector o : tssop ( ) : bcc
mb15e07sr 5 absolute maximum ratings warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol condition rating unit remark min max power supply voltage v cc ??0.55.5v v p ?v cc 6.0 v input voltage v i ??0.5v cc + 0.5 v output voltage v o except do gnd v cc v v o do gnd v p v storage temperature tstg ? ?55 +125 c parameter symbol value unit remark min typ max power supply voltage v cc 2.7 3.75 5.0 v v p v cc ?5.5v input voltage v i gnd ? v cc v operating temperature ta ?40 ? +85 c
mb15e07sr 6 electrical characteristics (v cc = 2.7 v to 5.0 v, ta = ?40 c to +85 c) *1: conditions; fosc = 13 mhz, vosc = 1.2 v pp , ta = +25 c, in locking state. *2: v cc = v p = 3.75 v, fosc = 13 mhz, vosc = 1.2 v pp , ta = +25 c, in power saving mode *3: ac coupling. 1000 pf capaci tor is connected under the condition of minimum operating frequency. *4: the symbol ??? (minus) means direction of current flow. *5: v cc = v p = 3.0 v, ta = +25 c (||i 3 | ? |i 4 ||) / [(|i 3 | + |i 4 |) /2] 100(%) (continued) parameter sym- bol condition value unit min typ max power supply current * 1 i cc * 1 f in = 2500 mhz, v cc = v p = 3.75 v ? 8.0 ? ma power saving current i ps ps = ?l? ? 0.1 * 2 20 a operating frequency fin f in 50 ? system 100 ? 2500 mhz osc in osc in ?3?40mhz input sensitivity fin * 3 pfin 100 mhz to 300 mhz ?6 ? +2 dbm 300 mhz to 2500 mhz ?15 ? +2 dbm osc in * 3 v osc ?0.5?v cc vp-p ?h? level input voltage data, clock, le, ps v ih ?v cc 0.7 ? ? v ?l? level input voltage v il ???v cc 0.3 ?h? level input current data, clock, le, ps i ih * 4 ??1.0?+1.0 a ?l? level input current i il * 4 ??1.0?+1.0 ?h? level input current osc in i ih ? 0 ? +100 a ?l? level input current i il * 4 ? ?100 ? 0 ?h? level output voltage ld/fout v oh v cc = v p = 3.75 v, i oh = ?1 ma v cc ? 0.4 ? ? v ?l? level output voltage v ol v cc = v p = 3.75 v, i ol = 1 ma ? ? 0.4 ?h? level output voltage do v doh v cc = v p = 3.75 v, i doh = ?0.5 ma v p ? 0.4 ? ? v ?l? level output voltage v dol v cc = v p = 3.75 v, i dol = 0.5 ma ? ? 0.4 high impedance cutoff current do i off v cc = v p = 3.75 v, v off = 0.5 v to v p ? 0.5 v ??2.5na ?h? level output current ld/fout i oh ????1.0 ma ?l? level output current i ol ?1.0?? ?h? level output current do i doh * 4 v cc = 3.75 v, v p = 3.75 v, v do = v p /2 ta = +25 c cs bit = ?1? ? ?4.0 ? ma cs bit = ?0? ? ?1.0 ? ?l? level output current i dol cs bit = ?1? ? 4.0 ? cs bit = ?0? ? 1.0 ? charge pump current rate i dol /i doh i domt * 5 v do = v p /2 ? 5 ? % vs v do i dovd * 6 0.5 v v do v p ? 0.7 v ? 10 ? % vs ta i dota * 7 ? 40 c ta +85 c?3?%
mb15e07sr 7 (continued) *6: v cc = v p = 3.0 v, ta = +25 c [(||i 2 | ? |i 1 ||) /2] / [(|i 1 | + |i 2 |) /2] 100(%) (applied to each i dol , i doh ) *7: v cc = v p = 3.0 v, v do = v p /2 (||i do(+85 c) | ? |i do(?40 c) || /2) / (|i do(+85 c) | + |i do(?40 c) | /2) 100(%) (applied to each i dol , i doh ) i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 charge pump output voltage (v) vp/2 vp vp ? 0.7 v
mb15e07sr 8 functional description 1. pulse swallow function the divide ratio can be calculated using the following equation: f vco = [(m n) + a] f osc r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14-bit pr ogrammable reference counter (3 to 16,383) m : preset divide ratio of modulus prescaler (32 or 64) 2. serial data input serial data is processed using the data, clock, and le pins. serial data controls the programmable reference divider and the programmable divider separately. binary serial data is entered through the data pin. one bit of data is shifted into the shift register on the rising edge of the clock. when the le signal pin is taken high, stored data is latched accordin g to the control bit data as follows: table 1. control bit (1) shift register configuration control bit (cnt) destination of serial data h for the programmable reference divider l for the programmable divider 12345678910111213141516171819 c n t r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 sw fc lds cs programmable reference counter msb data flow cnt : control bit [table 1] r1 to r14 : divide ratio setting bit for the programmable reference counter (3 to 16,383) [table 2] sw : divide ratio setting bit for th e prescaler (32/33 or 64/65) [table 5] fc : phase control bit for the phase comparator [table 8] lds : ld/f out signal select bit [table 7] cs : charge pump current select bit [table 6] note: start data input with msb first. lsb
mb15e07sr 9 table 2. binary 14-bit programmable reference counter data setting note : divide ratio less than 3 is prohibited. table 3. binary 11-bit programmable counter data setting note : divide ratio less than 3 is prohibited. divide ratio (r) r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 3 00 00 0000000011 4 00 00 0000000100 ? ?? ?? ?????????? 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 divide ratio (n)n11n10n9n8n7n6n5n4n3n2n1 3 00000000011 4 00000000100 ? ??????????? 2047 1 1111111111 12345678910111213141516171819 c n t a 1 a 2 a 3 a 4 a 5 a 6 a 7 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11 programmable counter lsb msb data flow cnt : control bit [table 1] n1 to n11: divide ratio setting bits for the programmable counter (3 to 2,047) [table 3] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table 4] note: data input with msb first.
mb15e07sr 10 table 4. binary 7-bit swallow counter data setting table 5. prescaler data setting table 6. charge pump current setting table 7. ld/fout output select data setting (2) relation between the fc input and phase characteristics the fc bit changes the phase characterist ics of the phase comparator. the in ternal charge pump output level (d o ) is reversed according to the fc bit. also, the monitor pin (f out ) output is controlled by the fc bit. the relationship between the fc bit and d o is shown below. table 8. fc bit data setting (lds = ?1?) *: high impedance divide ratio (a)a7a6a5a4a3a2a1 0 0000000 1 0000001 ? ??????? 127 1111111 sw prescaler divide ratio 1 32/33 0 64/65 cs current value 1 4.0 ma 0 1.0 ma lds ld/ f out output signal 1 fout signal 0 ld signal fc = 1 fc = 0 d o ld/fout d o ld/fout fr > f p h fout = fr l fout = fp fr < f p lh fr = f p z* z*
mb15e07sr 11 when designing a synthesizer, the fc pin sett ing depends on the vco and lpf characteristics. 3. power saving mode (intermittent mode control circuit) table 9. ps pin setting the intermittent mode control circui t reduces the pll power consumption. by setting the ps pin low, the device enters into the po wer saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do , becomes high impedance. for the signal pll, the lock detector, ld, remains high, indicating a locked condition. setting the ps pin high, releases the powe r saving mode, and the device works normally. the intermittent mode control circuit also ensures a smoo th startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comp arison frequency (fp) and the reference frequency (fr) which can cause a major change in the co mparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. ps pin status h normal mode l power saving mode (1 ) (2 ) when the lpf and vco characteristics are similar to (1), set fc bit high. when the vco characteristics are similar to (2), set fc bit low. vco output frequency lpf output voltage pll lpf vco note : give attention to the polarity for using active type lpf.
mb15e07sr 12 note: when power (v cc ) is first applied, the device must be in standby mode, ps = low, for at least 1 s. the serial data input after the power supply becames stable, and then the power saving mode is released after completed the data input. on off v cc c lock d ata l e p s (1) (2) (3) t v 1 s t ps 100 n s on off v cc c lock d ata l e p s (1) (2) (3) t v 1 s t ps 100 n s (1) ps = l (power saving mode) at power on (2) set serial data 1 s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps: l h) 100 ns later afte r setting serial data.
mb15e07sr 13 serial data input timing 1st data 2nd data control bit invalid data d ata c lock l e msb lsb t 1 t 2 t 3 t 6 t 5 t 4 t 7 note: le should be ?l? when the data is transferred into the shift register. parameter min typ max unit t 1 20 ? ? ns t 2 20 ? ? ns t 3 30 ? ? ns t 4 30 ? ? ns parameter min typ max unit t 5 100 ? ? ns t 6 20 ? ? ns t 7 100 ? ? ns on the rising edge of the clock, one bit of da ta is transferred into the shift register.
mb15e07sr 14 phase comparator output waveform fr fp ld d o d o t wu t wl notes : ? phase error detection range: ?2 to +2 ? pulses on do signal during locked state are output to prevent dead zone. ? ld output becomes low when phase is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. ? t wu and t wl depend on osc in input frequency. t wu > 2/fosc (s) (e. g. t wu > 153.8 ns, fosc = 13 mhz) t wu < 4/fosc (s) (e. g. t wl < 307.7 ns, fosc = 13 mhz) ? ld becomes high during the power saving mode (ps = ?l?). [fc = ?h?] [fc = ?l?]
mb15e07sr 15 measurment circuit (for measuring input sensitivity fin/osc in ) s.g. 50 ? 1000 pf s.g. 50 ? 1000 pf 0.1 f 0.1 f 86 43 1 9101112 14 75 2 13 15 16 1000 pf v cc fin xfin gnd d o v cc v p n.c. osc in clock data le ps n.c. ld / fout n.c. n.c. controller (setting divide ratio) oscilloscope note: tssop-16
mb15e07sr 16 n typical characteristics 1. fin input sensitivity 2. osc in input sensitivity 10 0 - 10 - 20 - 30 - 40 - 50 0 500 1000 1500 2000 2500 3000 3500 4000 ta = + 25 c v cc = 3.75 v v cc = 5.0 v v cc = 5.25 v spec v cc = 2.7 v input sensitivity - input frequency input sensitivity pfin (dbm) input frequency f in (mhz) catalog guaranteed range 10 0 - 10 - 20 - 30 - 40 - 50 0 20 40 60 80 100 120 140 180 ta = + 25 c v cc = 2.7 v v cc = 3.0 v v cc = 3.75 v v cc = 5.0 v spec 160 input sensitivity - input frequency input sensitivity v osc (dbm) input frequency f osc (mhz) catalog guaranteed range
mb15e07sr 17 3. do output current 10.00 ? 10.00 2.000 / div ta = + 25 c v cc = 3.75 v vp = 3.75 v 0.00 1.00 / div 7.00 10.00 ? 10.00 2.000 / div ta = + 25 c v cc = 3.75 v vp = 3.75 v 0.00 1.00 / div 7.00 ? 1.0 ma mode ? 4.0 ma mode i do - v do charge pump output voltage v do (v) charge pump output current i do (ma) i do - v do charge pump output voltage v do (v) charge pump output current i do (ma)
mb15e07sr 18 4. fin input impedance 5. osc in input impedance 78.328 ? ? 319.34 ? 300 mhz 22.145 ? ? 77.82 ? 1 ghz 14.324 ? 13.364 ? 2 ghz 1 : 2 : 3 : 22.184 ? 61.264 ? 3.9002 nh 1 4 3 2 start 300.000 000 mhz stop 2 500.000 000 mhz 4 2 500.000 000 mhz 633.5 ? ? 9.258 k ? 3 mhz 038.63 ? ? 3.0145 k ? 10 mhz 083.94 ? ? 1.5534 k ? 20 mhz 1 : 2 : 3 : 32.719 ? ? 801.28 ? 4.9656 pf 1 4 3 2 start 3.000 000 000 mhz stop 40.000 000 mhz 4 2 500.000 000 mhz
mb15e07sr 19 reference information (continued) s.g. spectrum analyzer osc in fin do lpf vco test circuit f vco = 1730 mhz k v = 42 mhz/v fr = 200 khz f osc = 13 mhz v cc =v p = 3.75 v v vco = 3.3 v ta = +25 c cp : 4.0 ma mod e 27 k ? 2.7 k ? 15000 pf 120 p f 1000 pf lpf ref ? 10.0 db mkr ? 200 khz ? 80.39 dbc center 1.732004 ghz span 1.00 mhz swp 23 s rbw 3 khz vbw 30 hz att 10 db delta mkr 200 khz noise/1 hz ? 116.53 dbc/hz vavg 10 ref ? 10.0 db mkr ? 1.00 khz ? 81.66 dbc/hz center 1.73200392 ghz span 10.00 khz swp 2.0 s rbw 30 hz vbw 100 hz delta mkr 1.00 khz noise/1 hz ? 81.66 dbc/hz att 10 db 10 10 ? pll reference leakage ? pll phase noise
mb15e07sr 20 (continued) 100.0050 mhz 2.88 khz/01v 99.99500 mhz 2.0000000 s 1730 mhz 1805 mhz within 1 khz lch hch 390 s 0 s ? mkr x : 389.98165 s y : 74.8653 mhz 100.0050 mhz 2.88 khz/01v 99.99500 mhz 2.0000000 s 0 s ? mkr x : 389.98165 s y : 74.8653 mhz 100.0050 mhz 2.88 khz/01v 99.99500 mhz 2.0000000 s 1805 mhz 1730 mhz within 1 khz hch lch 375 s 0 s ? mkr x : 375.00233 s y : ? 75.0818 mhz 250.0000 mhz 50.0000 mhz/01v 0 hz 2.0000000 s 0 s ? mkr x : 375.08233 s y : ? 75.0018 mhz
mb15e07sr 21 application example 0.1 f 1000 pf output lpf vco 16 15 14 13 12 11 10 9 123 4 56 78 0.1 f 1000 pf tcxo 1000 pf lock det. n.c. n.c. ld/fout n.c. clock mb15e07sr from a controller ps le data osc in n.c. v p v cc d o gnd xfin fin v p : 5.5 v max note : tssop-16
mb15e07sr 22 usage precautions to protect against damage by electrostatic di scharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting device into or removing device from a socket. -protect leads with a conductive sheet when transporting a board-mounted device. ordering information part number package remarks MB15E07SRPFT 16-pin, plastic tssop (fpt-16p-m07) mb15e07srpv1 16-pad, plastic bcc (lcc-16p-m06)
mb15e07sr 23 package dimensions (continued) 16-pin plastic tssop (fpt-16p-m07) note 1) *1 : resin protrusion. (each side : + 0.15 (.006) max) . note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width and pins th ickness include plating thickness. note 4) pins width do not incl ude tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2003 fujitsu limited f16020s-c-3-3 5.000.10(.197.004) 4.400.10 6.400.20 (.252.008) (.173.004) 0.10(.004) 0.65(.026) 0.240.08 (.009.003) 1 8 16 9 "a" 0.170.05 (.007.002) m 0.13(.005) details of "a" part 0~8 ? (.024.006) 0.600.15 (0.50(.020)) 0.25(.010) (.041.002) 1.050.05 (mounting height) 0.07 +0.03 ?0.07 +.001 ?.003 .003 (stand off) lead no. index * 1 * 2
mb15e07sr 24 (continued) 16-pad plastic bcc (lcc-16p-m06) dimensions in mm (inches) . note : the values in parentheses are reference values. c 1999 fujitsu limited c16017s-1c-1 0.3250.10 (.013.004) 3.40(.134)typ "a" 0.400.10 (.016.004) 2.45(.096) 0.80(.031) ref typ 4.550.10 (.179.004) 0.80(.031)max mounting height 0.0750.025 (.003.001) (stand off) 0.05(.002) 6 9 1 14 9 14 1 6 0.400.10 (.016.004) 0.750.10 (.030.004) details of "a" part 1.725(.068) ref 1.15(.045) ref "b" details of "b" part (.024.004) 0.600.10 (.024.004) 0.600.10 0.65(.026) typ index area (.134.004) 3.400.10
mb15e07sr fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0505 ? 2005 fujitsu limited printed in japan

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